Principal ASIC Design Engineer - Digital RTL & PHY Lead

Micron Technology; Folsom (CA); On-site; USD 186,000 - 407,000; Full time

Benefits offered by this job

Medical/dental/vision benefits

Paid time off and holidays

Equity and bonus opportunities

Job summary

Micron Technology is seeking a Principal ASIC Design Engineer to lead digital RTL design, synthesis, and timing closure across a front-to-back ASIC flow. You will own block architecture, CDC strategies, and the interface with layout.

Collaboration with verification, GLS, and lab bring-up teams will be essential. Your experience should include a complete tape-out and proficiency with Design Compiler/Genus, PrimeTime/Tempus, VCS/Xcelium, and DFT methods.

Qualifications

• BS, MS, or PhD in Electrical/Computer Engineering or related field.
• 7–12 years of ASIC design experience with at least one complete tape-out.
• Strong SystemVerilog RTL design coding practices and documentation.

Responsibilities

• Own digital block micro-architecture, RTL, and interface control documents.
• Define CDC strategy and coordinate with analog/design teams for chip integration.
• Drive synthesis, timing closures, and maintain SDC constraints across corners.
• Interface with layout teams, provide netlists, constraints, and design intent.
• Write SystemVerilog Assertions and support block-level verification planning.
• Contribute to GLS timing simulations, lab bring-up, and debug activities.

Job description

Micron Technology is seeking a Principal ASIC Design Engineer to lead digital RTL design, synthesis, and timing closure across a front-to-back ASIC flow. You will own block architecture, CDC strategies, and the interface with layout.

Collaboration with verification, GLS, and lab bring-up teams will be essential. Your experience should include a complete tape-out and proficiency with Design Compiler/Genus, PrimeTime/Tempus, VCS/Xcelium, and DFT methods.