Principal Engineer, ASIC Physical Design

Micron Technology; Minneapolis (MN); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Medical, Dental and Vision plans

Paid time-off and holidays

Paid family leave

Job summary

Micron Technology is seeking a seasoned ASIC Engineer to lead block-level and full-chip physical design, including floorplanning, placement, CTS, routing, and tape-out for DRAM tester solutions. You will drive timing closure across modes and corners, ensure power integrity, and support signoff through IR/EM analyses on advanced nodes.

The role emphasizes developing efficient APR flows and automation, owning closure work, and coordinating with cross-functional teams for successful tape-out across

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or Computer Architecture.
• Minimum of 15 years of hands-on ASIC physical design implementation experience.
• Proven experience with multiple production tape-outs in advanced process nodes.
• Strong expertise in low-power design techniques including UPF/CPF and multi-voltage systems.
• Proficiency in scripting languages such as Tcl, Perl, or Python for flow automation.

Responsibilities

• Lead block-level and full-chip physical design including floorplanning, placement, CTS, routing, and tape-out.
• Drive timing closure across multiple modes and corners using industry-standard STA tools.
• Perform power integrity, IR/EM, and power grid closure to meet signoff requirements.
• Develop and optimize APR flows, scripts, and methodologies for PPA improvements.
• Own subsystem or full-chip closure work while coordinating with cross-functional teams.

Skills

ASIC physical design

Timing closure

Low-power design

Scripting for flows

Education

Bachelor's or Master’s in Electrical Engineering / Electronics / Computer Architecture

Tools

Synopsys tools

Cadence tools

Calibre

Job description

Job Summary

This position supports Micron’s DRAM Tester Solutions group, focusing on physical design implementation for processors, controller architectures, and ASICs. The role is responsible for full‑chip and block‑level physical design closure, low‑power implementation, timing, power, and signal integrity signoff, and successful tape‑out across advanced technology nodes.

Responsibilities

• Lead block‑level and full‑chip physical design including floorplanning, placement, CTS, routing, and tape‑out.
• Drive timing closure across multiple modes and corners using industry‑standard STA tools.
• Perform power integrity, IR/EM, and power grid closure to meet signoff requirements.
• Develop and optimize APR flows, scripts, and methodologies for PPA improvements.
• Own subsystem or full‑chip closure work while coordinating with cross‑functional teams.

Minimum Qualifications

• Bachelor’s degree or Master’s degree or equivalent experience in Electrical Engineering, Electronics, or Computer Architecture.
• Minimum of 15 years of hands‑on ASIC physical design implementation experience.
• Proven experience with multiple production tape‑outs in advanced process nodes.
• Strong expertise in low‑power design techniques including UPF/CPF and multi‑voltage systems.
• Proficiency in scripting languages such as Tcl, Perl, or Python for flow automation.

Preferred Qualifications

• Experience with Synopsys and Cadence physical design and timing tools.
• Hands‑on physical verification closure using Calibre and power integrity analysis tools.
• Experience with IR/EM signoff and resolution at block and full‑chip level.
• Background in memory tester designs, high‑speed interfaces, or microprocessor architectures.
• Experience developing and enabling APR flows for new technology nodes.

Job Profile(s)

ASIC Engineer 5

Relocation Level

TBD

Benefits

Micron offers a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays.

EEO Statement

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.