Senior ASIC Physical Design Lead

Micron Technology, Inc.

Minneapolis (MN)

Hybrid

USD 180,000 - 240,000

Full time

14 days+
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Job summary

Micron Technology, Inc. in Minneapolis, MN, is seeking a Principal Engineer to lead ASIC physical design for DRAM tester solutions.

The role covers full‑chip and block‑level closure, low‑power implementation, timing, power, and SI signoff, with tape‑out across advanced nodes. You will drive floorplanning, placement, CTS, routing, and timing closure using STA tools, while mentoring cross‑functional teams and advancing APR flows for PPA improvements.

Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or Computer Architecture.
  • 15+ years of hands-on ASIC physical design implementation experience.
  • Multiple production tape-outs in advanced process nodes.
  • Strong UPF/CPF low-power design expertise.
  • Proficiency in Tcl, Perl, or Python for flow automation.

Responsibilities

  • Lead block-level and full-chip physical design including floorplanning, placement, CTS, routing, and tape-out.
  • Drive timing closure across multiple modes and corners using STA tools.
  • Perform power integrity, IR/EM, and power grid closure to meet signoff requirements.
  • Develop and optimize APR flows, scripts, and methodologies for PPA improvements.
  • Coordinate with cross-functional teams to own subsystem or full-chip closure.

Skills

ASIC PD
Tcl/Python/Perl
Timing closure
UPF/CPF
STA tooling

Education

Bachelors or Masters in EE/ Electronics/ Computer Architecture

Tools

Synopsys PD tools
Cadence PD tools
Calibre

Job description

Micron Technology, Inc. in Minneapolis, MN, is seeking a Principal Engineer to lead ASIC physical design for DRAM tester solutions.

The role covers full‑chip and block‑level closure, low‑power implementation, timing, power, and SI signoff, with tape‑out across advanced nodes. You will drive floorplanning, placement, CTS, routing, and timing closure using STA tools, while mentoring cross‑functional teams and advancing APR flows for PPA improvements.

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