Senior ASIC/SoC Physical Design Architect

Qualcomm Incorporated; Santa Clara (CA); On-site; USD 190,000 - 285,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks seasoned Physical Design Engineers to contribute to SoC/ASIC projects across HPC, AI, mobile, automotive, and data center domains.

You will work on floorplanning, CTS, low-power implementation, and timing closure with world-class teams. The role spans collaboration with architecture, RTL, DFT, verification, and methodology groups, delivering innovative low-power methodologies and automated place-and-route solutions.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 10+ years of industry experience or relevant academic/project experience in Physical Design.

Responsibilities

• Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
• Develop physical design solutions for complex high-speed ASICs and SoCs.
• Perform floorplanning, partitioning, power planning, and IR-drop analysis.
• Execute placement, CTS, routing, timing optimization, and timing closure across MMMC scenarios.
• Analyze and resolve timing violations and signal integrity issues.

Skills

Python

Perl

TCL

Shell scripting

C/C++

Linux/Unix

Education

Electrical Engineering (B.S.)

Computer Engineering (B.S.)

Computer Science (B.S.)

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PrimeTime SI

Job description

Qualcomm Technologies, Inc. seeks seasoned Physical Design Engineers to contribute to SoC/ASIC projects across HPC, AI, mobile, automotive, and data center domains.

You will work on floorplanning, CTS, low-power implementation, and timing closure with world-class teams. The role spans collaboration with architecture, RTL, DFT, verification, and methodology groups, delivering innovative low-power methodologies and automated place-and-route solutions.