Lead Full-Chip ASIC Physical Design Engineer

020 Cisco Systems, Inc.; San Jose (CA); On-site; USD 251,000 - 363,000; Full time

Benefits offered by this job

Medical, dental and vision insurance

401(k) plan with Cisco matching

Paid parental leave

Disability coverage

Life insurance

Restricted stock units

Paid holidays

Wellness days

Vacation and sick time

Job summary

Cisco Systems, Inc. Common Hardware Group (CHG) is seeking a senior ASIC design professional to lead fullchip floorplanning and signoff across 7nm/5nm tech nodes.

You will collaborate with RTL/DFT, EDA vendors and foundries to optimize performance, area, and power while driving state-of-the-art integration flows. The role emphasizes architecture understanding, IP placement, and hierarchical design with a strong emphasis on clocking and power integrity.

Qualifications

• Bachelor’s degree in Engineering and 15+ years of ASIC related experience.
• Master’s degree in Engineering and 12+ years of ASIC related experience, or PhD in Engineering and 7+ years of ASIC related experience.

Responsibilities

• Understand architecture of the design, IP placement constraints and fullchip floorplan.
• Collaborate with system and package design teams to implement the fullchip floorplan.
• RTL-to-GDSII flow: floorplan, power grid, place & route, timing, signoff.
• Improve design methodology by analyzing tool flows and implementing enhancements.
• Coordinate with RTL, DFT, EDA vendors and tool/flow teams for best-in-class design.

Skills

ASIC design experience

RTL2GDSII flow

Floorplanning

Timing closure

Python

AI design tools

Team collaboration

Education

Bachelor’s degree in Engineering

Master’s degree in Engineering

PhD in Engineering

Tools

Innovus

Tempus

Primetime

Calibre

Redhawk

Voltus

Job description

Cisco Systems, Inc. Common Hardware Group (CHG) is seeking a senior ASIC design professional to lead fullchip floorplanning and signoff across 7nm/5nm tech nodes.

You will collaborate with RTL/DFT, EDA vendors and foundries to optimize performance, area, and power while driving state-of-the-art integration flows. The role emphasizes architecture understanding, IP placement, and hierarchical design with a strong emphasis on clocking and power integrity.