Senior ASIC RTL Design Engineer for High-Performance Chips

CyberCoders, Inc.; Sunnyvale (CA); On-site; USD 280,000 - 580,000; Full time

Job summary

CyberCoders, Inc. is seeking an experienced ASIC Design Engineer (Senior/Staff/Principal) for on-site roles in San Jose, CA or Colorado Springs, CO.

This position focuses on RTL design for high-performance ASICs, owning blocks from spec through bring-up, with opportunities to impact AI data center silicon. You will work with cross-disciplinary teams to optimize timing, power and area, delivering silicon that ships in data center products.

Qualifications

• Deep hands-on Verilog/SystemVerilog RTL experience.
• Strong track record in digital IC design.
• Experience taking designs through timing closure.

Responsibilities

• Translate architecture specs into detailed microarchitecture and design documents.
• Write clean, high-performance Verilog/SystemVerilog for complex logic including pipelined datapaths and multi-clock domains.
• Integrate third-party IP into blocks and ensure compatibility with the rest of the chip.
• Drive timing closure and optimize power, performance, and area (PPA).
• Diagnose and fix design issues from simulation to post-silicon.
• Participate in silicon bring-up and validation activities.
• Collaborate daily with verification, firmware, software, emulation and validation teams across the ASIC lifecycle.

Skills

Verilog/SystemVerilog

Digital IC design

Timing closure

Microarchitecture

Team ownership

Job description

CyberCoders, Inc. is seeking an experienced ASIC Design Engineer (Senior/Staff/Principal) for on-site roles in San Jose, CA or Colorado Springs, CO.

This position focuses on RTL design for high-performance ASICs, owning blocks from spec through bring-up, with opportunities to impact AI data center silicon. You will work with cross-disciplinary teams to optimize timing, power and area, delivering silicon that ships in data center products.