Senior ASIC Physical Design Engineer (SoC/AI)

QUALCOMM, Inc.; Santa Clara (CA); On-site; USD 190,000 - 285,000; Full time

Job summary

Qualcomm Technologies, Inc. in Santa Clara, CA is seeking talented Physical Design Engineers to join our growing SoC and ASIC Design organization.

You will drive all stages of the physical design flow for high-performance ASICs/SoCs, including floorplanning, CTS, routing, and timing closure across MMMC scenarios. You will collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution and sign-off.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 6+ years of ASIC design/verification/validation/integration experience (or 5+ with Master’s, 4+ with PhD).
• Experience in ASIC/SoC physical design implementation including floorplanning, CTS, routing, and timing closure.
• Experience with Cadence Innovus and/or Synopsys Fusion Compiler; timing analysis with PrimeTime SI.
• Knowledge of low-power design, clock-tree synthesis, and DFT-aware flows.
• Strong scripting in Python/Perl/TCL and Linux environment.

Responsibilities

• Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
• Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
• Perform floorplanning, partitioning, power planning, and IR-drop analysis.
• Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across MMMC scenarios.
• Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
• Perform RC extraction, physical verification, and formal verification activities.
• Implement ECOs and support design convergence through sign-off.
• Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
• Contribute to the development of innovative low-power implementation methodologies and customized place-and-route solutions.
• Develop automation and productivity tools using scripting languages and software development techniques.

Skills

C/C++

Python

Linux/Unix

Shell scripting

Perl

TCL

Problem solving

Education

Bachelor's in Electrical/Computer Engineering or CS

Master's in related field

PhD in related field

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PrimeTime SI

Job description

Qualcomm Technologies, Inc. in Santa Clara, CA is seeking talented Physical Design Engineers to join our growing SoC and ASIC Design organization.

You will drive all stages of the physical design flow for high-performance ASICs/SoCs, including floorplanning, CTS, routing, and timing closure across MMMC scenarios. You will collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution and sign-off.