Senior ASIC Packaging SI/PI Lead — Remote‑Eligible

Cisco Systems, Inc; Allentown (Lehigh County); Hybride; USD 187 000 - 268 000; Plein temps

Avantages offerts par ce poste

Health benefits

Résumé du poste

Cisco Systems, Inc. is seeking a Signal and Power Integrity Technical Lead in the San Jose, CA area. The role focuses on developing next-generation ASIC packaging, analyzing SI/PI, and defining methods for high-performance packaging across interposer, substrate, and PCB.

You will mentor teams and drive design reviews across multi-disciplined engineering groups. The candidate will lead architecture discussions and contribute to chip design and verification, with emphasis on 2.5D packaging

Qualifications

• Bachelor's degree in Electrical Engineering with 8+ years SI/PI experience.
• Experience with high-speed design principles, 56G PAM4 SerDes, channel modeling, BER.
• Proficiency with pre- and post-layout SI/PI simulations (Cadence Sigrity, HFSS, Keysight ADS).
• Layout review and physical validation using Cadence APD/Ansys EM flows.
• SPICE-based circuit analysis for modeling and validation.

Responsabilités

• Develop, document, and implement design rules for ultra-high-speed signaling.
• Analyze substrate SI/PI and advise on optimal solutions with layout teams.
• Design ASIC packages for high-volume release, including post-layout extraction.
• Collaborate with partners to resolve complex technical issues.
• Define processes and tools for complex ASIC/package developments.
• Lead architecture discussions and design of high-performance ASICs.
• Mentor SI team and promote design-review culture.

Connaissances

High-speed design

SI/PI simulation

Layout review

Circuit analysis

56G SerDes

Formation

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

PhD in Electrical Engineering

Outils

Cadence Sigrity

Ansys HFSS

Keysight ADS

Cadence APD

Ansys EM Flow

Description du poste

Cisco Systems, Inc. is seeking a Signal and Power Integrity Technical Lead in the San Jose, CA area. The role focuses on developing next-generation ASIC packaging, analyzing SI/PI, and defining methods for high-performance packaging across interposer, substrate, and PCB.

You will mentor teams and drive design reviews across multi-disciplined engineering groups. The candidate will lead architecture discussions and contribute to chip design and verification, with emphasis on 2.5D packaging