Remote Lead, ASIC Packaging SI/PI & Design

Cisco Systems, Inc; San Jose (CA); Remote; USD 187,000 - 268,000; Full time

Job summary

Cisco Silicon One in San Jose is seeking a Signal and Power Integrity Technical Lead to drive packaging development for high-performance ASICs. This role allows remote work within the United States and focuses on ultra-high-speed design, SI/PI analysis, and collaboration across layout, packaging, and system teams.

You will mentor junior engineers, define design rules for 56G PAM4 SerDes, perform post-layout extraction, and lead architecture reviews to ensure power, signal integrity, and

Qualifications

• Bachelor's degree in Electrical Engineering with 8+ years of SI/PI experience, or Master's with 6+ years, or PhD with 3+ years.
• Experience with high-speed design principles, including 56G PAM4 SerDes, channel modeling, and BER prediction.
• Proficiency in SI/PI simulations using Cadence Sigrity, Ansys HFSS, Keysight ADS.
• Layout reviews and physical validation using Cadence APD and Ansys EM flows.
• Circuit analysis with SPICE.

Responsibilities

• Develop and validate ASIC packages for high-volume production including post-layout extraction.
• Analyze substrate SI/PI and collaborate with layout to optimize interposer, substrate, and PCB designs.
• Document and implement design rules for ultra-high-speed signaling meeting power/performance/area goals.
• Lead architecture discussions for high-performance ASICs and reviews of intricate IC designs.
• Mentor SI team and promote design reviews and continuous improvement.

Skills

High-Speed Design Theory

SI/PI Simulation

Layout Review

Circuit Analysis

Mentoring

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Keysight ADS

Cadence APD

Ansys EM flows

SPICE

Job description

Cisco Silicon One in San Jose is seeking a Signal and Power Integrity Technical Lead to drive packaging development for high-performance ASICs. This role allows remote work within the United States and focuses on ultra-high-speed design, SI/PI analysis, and collaboration across layout, packaging, and system teams.

You will mentor junior engineers, define design rules for 56G PAM4 SerDes, perform post-layout extraction, and lead architecture reviews to ensure power, signal integrity, and