Senior ASIC Engineer – SoC, ML & Network Acceleration

Meta; Lansing (MI); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta in the Infrastructure organization is hiring ASIC Design Engineers to build cutting edge ASICs for machine learning, video transcoding and network acceleration. Responsibilities include architecture exploration, micro-architecture development, IP identification and integration, and collaboration with verification, emulation, and implementation teams to close timing and power on complex IPs.

Strong RTL skills with Verilog/SystemVerilog and experience in SoC micro-architecture are required;

Qualifications

• Bachelor's degree in CS/CE or equivalent.
• 8+ years of micro-architecture and RTL experience for complex IPs or SoC integration.
• RTL development using Verilog, SystemVerilog and HLS.

Responsibilities

• Architecture exploration and micro-architecture development.
• Identify and integrate soft and hard IP; collaborate with verification and emulation teams on test plans and debugging.
• Collaborate with implementation to meet timing and power targets.

Skills

ASIC design

RTL development

SystemVerilog

Verilog

HLS

SoC micro-architecture

IP integration

Timing closure

Education

Bachelor's degree in Computer Science, Computer Engineering, or related field

Master's or PhD in Electrical Engineering or Computer Science (preferred)

Job description

Meta in the Infrastructure organization is hiring ASIC Design Engineers to build cutting edge ASICs for machine learning, video transcoding and network acceleration. Responsibilities include architecture exploration, micro-architecture development, IP identification and integration, and collaboration with verification, emulation, and implementation teams to close timing and power on complex IPs.

Strong RTL skills with Verilog/SystemVerilog and experience in SoC micro-architecture are required;