Senior ASIC Architect for SoC & ML Hardware

Meta; Phoenix (AZ); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is hiring ASIC Design Engineers in our Infrastructure organization to build cutting edge ASICs for machine learning, video transcoding and network acceleration.

Role involves architecture exploration, micro-architecture development and IP integration, with collaboration across verification, emulation, and implementation teams to close timing and power gaps. Positions require deep RTL experience (Verilog/SystemVerilog/HLS) and a strong SoC background.

Qualifications

• Bachelor's degree in CS/CE or equivalent.
• 8+ years in micro-architecture & RTL or SoC integration experience.
• RTL development using Verilog, SystemVerilog and HLS.

Responsibilities

• Architecture exploration and micro-architecture development for ASIC designs.
• Identify and integrate soft and hard IP; collaborate with verification/emulation teams on test plans and debugging.
• Collaborate with implementation to meet timing and power targets.

Skills

Architecture exploration

Micro-architecture development

IP identification & integration

Collaboration with verification & emu

Timing & power closure collaboration

Education

Bachelor's degree or equivalent in CS/CE/related field

8+ years micro-architecture & RTL or SoC integration

RTL development: Verilog, SystemVerilog, HLS

Job description

Meta is hiring ASIC Design Engineers in our Infrastructure organization to build cutting edge ASICs for machine learning, video transcoding and network acceleration.

Role involves architecture exploration, micro-architecture development and IP integration, with collaboration across verification, emulation, and implementation teams to close timing and power gaps. Positions require deep RTL experience (Verilog/SystemVerilog/HLS) and a strong SoC background.