Senior ASIC Design Engineer — ML/Video Acceleration Equity

Meta; Trenton (NJ); Vor Ort; USD 178.000 - 250.000; Vollzeit

Zusammenfassung

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs for machine learning, video transcoding and network acceleration. You will explore architectures, develop micro-architectures, identify and integrate soft and hard IP, and collaborate with verification, emulation and implementation teams to meet timing and power goals.

Minimum qualifications include a Bachelor's degree in CS/CE or related field and 8+ years in micro-architecture/RTL;

Qualifikationen

• Bachelor's degree in Computer Science, Computer Engineering, a related technical field, or equivalent practical experience.
• 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs or experience in SoC micro-architecture, design and integration.
• RTL development using Verilog, SystemVerilog and HLS.

Aufgaben

• Architecture exploration.
• Micro-architecture development.
• Soft and hard IP identification, selection and integration; collaboration with verification and emulation teams in test plan development and debug.
• Collaboration with implementation team to close the design on timing and power.

Kenntnisse

Architecture exploration

Micro-architecture development

IP integration

Ausbildung

Bachelor's degree in CS/CE or related field

Tools

Verilog

SystemVerilog

HLS

Jobbeschreibung

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs for machine learning, video transcoding and network acceleration. You will explore architectures, develop micro-architectures, identify and integrate soft and hard IP, and collaborate with verification, emulation and implementation teams to meet timing and power goals.

Minimum qualifications include a Bachelor's degree in CS/CE or related field and 8+ years in micro-architecture/RTL;