Senior ASIC Design Engineer - ML/Video Acceleration, Equity

Meta; Austin (TX); On-site; USD 178,000 - 250,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is hiring ASIC Design Engineers to build cutting-edge ASICs for ML, video transcoding, and network acceleration. The role focuses on architecture exploration, micro-architecture development, and IP identification and integration with verification and emulation teams.

Strong RTL skills in Verilog/SystemVerilog and HLS are required. Experience with SoC architectures and expertise in timing closure are highly valued.

Qualifications

• Bachelor's degree or equivalent practical experience in CS/CE or related field.
• 8+ years in micro-architecture and RTL development for complex IPs OR SoC micro-architecture, design and integration.
• RTL development using Verilog, SystemVerilog and HLS.

Responsibilities

• Architecture exploration
• Micro-architecture development
• Soft and hard IP identification, selection and integration with verification/emulation teams
• Collaborate with implementation to meet timing and power targets

Skills

RTL development

Verilog/SystemVerilog

HLS

SoC architecture

Timing closure

IP integration

Education

Bachelor's degree in CS/CE or related field

MS/PhD preferred

Electrical Engineering background

Job description

Meta is hiring ASIC Design Engineers to build cutting-edge ASICs for ML, video transcoding, and network acceleration. The role focuses on architecture exploration, micro-architecture development, and IP identification and integration with verification and emulation teams.

Strong RTL skills in Verilog/SystemVerilog and HLS are required. Experience with SoC architectures and expertise in timing closure are highly valued.