Senior ASIC Design Engineer — ML & Network Acceleration

Meta; Lincoln (NE); On-site; USD 178,000 - 250,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration. The role focuses on architecture exploration, RTL development, and IP integration, with collaboration across verification, emulation and implementation teams to optimize timing and power.

Strong Verilog/SystemVerilog capabilities and IP integration experience are expected, with competitive bonuses, equity, and

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or related field
• 8+ years in micro-architecture and RTL development or SoC micro-architecture/design & integration
• RTL development using Verilog, SystemVerilog and HLS

Responsibilities

• Architecture exploration for ASIC designs
• Micro-architecture development
• Identify, select and integrate soft/hard IP; collaborate with verification and emulation teams on test plans and debugging
• Collaborate with implementation to meet timing and power goals

Skills

Architecture exploration

Micro-architecture development

IP identification & integration

Collaboration with timing/power

Education

Bachelor's degree in CS/CE or equivalent

8+ years in micro-architecture/RTL or SoC IP design

RTL: Verilog/SystemVerilog/HLS

Tools

Verilog

SystemVerilog

HLS

Job description

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration. The role focuses on architecture exploration, RTL development, and IP integration, with collaboration across verification, emulation and implementation teams to optimize timing and power.

Strong Verilog/SystemVerilog capabilities and IP integration experience are expected, with competitive bonuses, equity, and