Senior ASIC Design Engineer for ML/Video Acceleration

Meta; Topeka (KS); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

The role emphasizes architecture exploration, micro-architecture development and IP integration, with collaboration across verification, emulation and implementation teams to meet timing and power goals.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration.
• RTL development using Verilog, System Verilog and HLS.

Responsibilities

• Architecture exploration and micro-architecture development for ASIC designs.
• Soft and hard IP identification, selection and integration, coordinating with verification and emulation teams for test plan development and debugging.
• Collaboration with implementation teams to meet timing and power targets and close the design on timing.

Skills

Micro-architecture

RTL development

SoC integration

Education

Bachelor's degree

Tools

Verilog

SystemVerilog

HLS

Job description

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

The role emphasizes architecture exploration, micro-architecture development and IP integration, with collaboration across verification, emulation and implementation teams to meet timing and power goals.