Senior ASIC Design Engineer – RTL, SoC & CPU Subsystems

Meta; Olympia (WA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is hiring ASIC Design Engineers in our Infrastructure organization to build cutting-edge ASICs for machine learning, video transcoding, and network acceleration.

The role focuses on architecture exploration, micro-architecture development, and IP selection and integration with verification teams to ensure proper test plans and debugging. Collaboration with the implementation team targets timing and power optimizations.

Qualifications

• Bachelor's degree or equivalent in a technical field is required.
• 8+ years in micro-architecture and RTL development for complex IPs or SoC micro-architecture experience.
• RTL development using Verilog, SystemVerilog and HLS.

Responsibilities

• Architecture exploration and micro-architecture development.
• Identification, selection and integration of soft and hard IP, coordinating with verification and emulation teams for test plans and debugging.
• Collaborate with implementation team to meet timing and power goals.

Skills

RTL development

Verilog

SystemVerilog

HLS

SoC micro-architecture

IP integration

Education

Bachelor's degree in CS/CE or equivalent

Tools

Verilog

SystemVerilog

HLS

Job description

Meta is hiring ASIC Design Engineers in our Infrastructure organization to build cutting-edge ASICs for machine learning, video transcoding, and network acceleration.

The role focuses on architecture exploration, micro-architecture development, and IP selection and integration with verification teams to ensure proper test plans and debugging. Collaboration with the implementation team targets timing and power optimizations.