Senior ASIC Design Engineer - ML & Network Acceleration

Meta; Atlanta (GA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is seeking an experienced ASIC Design Engineer to join the Infrastructure organization, building cutting-edge chips for ML, video transcoding and network acceleration.

You'll lead architecture exploration, micro-architecture work, and IP integration, collaborating with verification, emulation and implementation teams to meet timing and power goals, with 178k–250k USD compensation and equity.

Qualifications

• Bachelor's degree in CS/CE or equivalent practical experience.
• 8+ years in micro-architecture and RTL development for complex IPs or SoC integration.
• RTL development using Verilog, SystemVerilog and HLS.

Responsibilities

• Architecture exploration and micro-architecture development.
• Identify, select and integrate soft/hard IP; collaborate with verification and emulation teams.
• Collaborate with implementation teams to meet timing and power targets.

Skills

Micro-architecture

RTL development

Verilog

SystemVerilog

HLS

Education

Bachelor's degree in Computer Science or Electrical Engineering or related field

Master’s degree or PhD preferred

Tools

Synthesis tools

Timing closure

Formal verification

Job description

Meta is seeking an experienced ASIC Design Engineer to join the Infrastructure organization, building cutting-edge chips for ML, video transcoding and network acceleration.

You'll lead architecture exploration, micro-architecture work, and IP integration, collaborating with verification, emulation and implementation teams to meet timing and power goals, with 178k–250k USD compensation and equity.