ASIC Design Engineer for ML & Networking Acceleration

Meta; Denver (CO); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Required qualifications include 8+ years in micro-architecture/RTL development and RTL work with Verilog, SystemVerilog or HLS, along with a Bachelor's degree in a related field. Public compensation ranges from $178,000 to $250,000 plus bonus, equity and benefits.

Qualifications

• Bachelor's degree in CS/CE or related field.
• 8+ years in micro-architecture and RTL for complex IPs or SoC micro-architecture.
• RTL development using Verilog, SystemVerilog and HLS.

Responsibilities

• Architecture exploration to define design approach.
• Micro-architecture development for complex IPs.
• Identify and integrate soft and hard IP with verification teams.
• Collaborate with implementation to meet timing and power targets.

Skills

Architecture exploration

Micro-architecture development

IP identification and integration

Collaboration with verification and em

Education

Bachelor's degree in Computer Science, Computer Engineering or related field

Master’s or PhD in Electrical Engineering, Computer Science or related areas

Tools

Verilog

SystemVerilog

HLS

Job description

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Required qualifications include 8+ years in micro-architecture/RTL development and RTL work with Verilog, SystemVerilog or HLS, along with a Bachelor's degree in a related field. Public compensation ranges from $178,000 to $250,000 plus bonus, equity and benefits.