Senior ASIC DFT & STA Timing Engineer

Cisco Systems, Inc; San Jose (CA); On-site; USD 168,000 - 245,000; Full time

Job summary

Cisco Systems, Inc. is seeking an ASIC DFT STA Engineer in the Silicon One development organization. You will be a detail-oriented engineer with strong timing expertise, collaborating with cross-functional teams to manage clocks, constraints, and DFT flows.

The role centers on driving DFT and quality through the full implementation flow and post-silicon validation. You will interact with teams across RTL, timing, and physical design while applying SDC debugging and STA tool proficiency to

Qualifications

• Bachelors + 7 years of related experience, or Masters + 4 years, or PhD + 1 year.
• Experience with RTL design, CDC/RDC and conformal verification.
• Experience in timing constraint development and verification.
• Scripting in Perl, TCL, Python, or Makefile (at least 2).
• Masters degree + 10 years of relevant experience (preferred).
• Experience with PCIe timing constraints, TSMC memory timing.

Responsibilities

• Lead the DFT and quality process through the implementation flow.
• Support post-silicon validation phases with exposure to physical design signoff.
• Collaborate with cross-functional teams to review timing data and constraints.
• Drive timing closure and debugging of timing issues across designs.

Skills

RTL design

CDC/RDC

Conformal verification

SDC development

Timing constraints

Perl

TCL

Python

Makefile

Education

Bachelor's degree 7+ yrs experience

Master's degree 4+ yrs experience

PhD 1+ yr experience

Tools

Fusion Compiler

Primetime

Tessent

Job description

Cisco Systems, Inc. is seeking an ASIC DFT STA Engineer in the Silicon One development organization. You will be a detail-oriented engineer with strong timing expertise, collaborating with cross-functional teams to manage clocks, constraints, and DFT flows.

The role centers on driving DFT and quality through the full implementation flow and post-silicon validation. You will interact with teams across RTL, timing, and physical design while applying SDC debugging and STA tool proficiency to