Senior ASIC DFT & DV Engineer (Hybrid)

Cisco Systems, Inc; San Jose (CA); Hybrid; USD 168,000 - 245,000; Full time

Job summary

Cisco Systems, Inc.- Silicon One team is looking for a seasoned test engineer to lead DFT planning, develop test benches, and verify complex silicon designs. The role emphasizes collaboration with design, verification, and PD teams to ensure robust test coverage across ATE screening and in-system diagnostics.

The candidate will contribute to innovative hardware DFT strategies for new silicon models, including bare die and stacked die layouts, while crafting reusable debug methods and ensuring

Qualifications

• Bachelor’s in Electrical Engineering or equivalent with 7+ years (or Master’s with 4+ years) of experience.
• Experience in test planning based on complex design specifications.
• Experience in testbench development using SystemVerilog.

Responsibilities

• Plan tests and develop benches to verify DFT architecture for ATE screening and in-system test.
• Collaborate with design, design verification and PD teams to integrate test logic.
• Develop innovative hardware DFT/test strategies for new silicon, bare die and stacked die.
• Craft solutions and debug efficiently with the team.

Skills

Test planning

Testbench development

SystemVerilog

DVE Verdi

TCL/Python/Perl

UVM

JTAG/MBIST

Education

Electrical Engineering degree

Job description

Cisco Systems, Inc.- Silicon One team is looking for a seasoned test engineer to lead DFT planning, develop test benches, and verify complex silicon designs. The role emphasizes collaboration with design, verification, and PD teams to ensure robust test coverage across ATE screening and in-system diagnostics.

The candidate will contribute to innovative hardware DFT strategies for new silicon models, including bare die and stacked die layouts, while crafting reusable debug methods and ensuring