Senior ASIC DFT STA Engineer - Timing & Validation

020 Cisco Systems, Inc.; San Jose (CA); On-site; USD 168,000 - 245,000; Full time

Job summary

Cisco Systems, Inc. is seeking an ASIC DFT STA Engineer to join the Silicon One development organization in San Jose.

You will drive timing constraints, DFT/STA strategies, and work across RTL design, CDC/RDC, and verification efforts to enable successful post-silicon validation. You will collaborate with diverse teams, contribute to design signoff activities, and help deliver next-generation networking chips for a global customer base.

Qualifications

• Bachelor's degree with 7+ years of related experience, or Master's with 4+ years, or PhD with 1 year.
• Experience with RTL design, CDC/RDC and conformal verification.
• Proficiency in timing constraint development and verification; scripting in Perl/TCL/Python/Makefile.

Responsibilities

• Lead DFT/STA processes through the full implementation flow and post-silicon validation.
• Collaborate with cross-functional teams to analyze timing data and constraints.
• Assist with physical design signoff activities.

Skills

RTL design

CDC/RDC

Conformal verification

SDC development

Timing constraints

Perl

TCL

Python

Makefile

Education

Bachelor's degree

Master's degree

PhD in related field

Tools

Synopsys Fusion/Design Compiler

Tessent (DFT)

Primetime

Synthesis tools

Job description

Cisco Systems, Inc. is seeking an ASIC DFT STA Engineer to join the Silicon One development organization in San Jose.

You will drive timing constraints, DFT/STA strategies, and work across RTL design, CDC/RDC, and verification efforts to enable successful post-silicon validation. You will collaborate with diverse teams, contribute to design signoff activities, and help deliver next-generation networking chips for a global customer base.