Lead ASIC STA & DFT Engineer

020 Cisco Systems, Inc.; San Jose (CA); On-site; USD 187,000 - 268,000; Full time

Job summary

Cisco Systems, Inc. in the United States is seeking an ASIC DFT STA Technical Lead.

You will be a detail-oriented STA engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups and exceptions, collaborating with cross-functional teams across design and verification to drive efficient timing closure. You will lead DFT and quality processes through the full implementation flow and post-silicon validation, with exposure to physical design signoff

Qualifications

• Bachelors degree with 8+ years of related experience, or equivalent education.
• Experience RTL design, CDC/RDC, and conformal verification.
• Timing constraint development and verification experience.

Skills

RTL design

CDC/RDC verification

Conformal verification

Timing constraints development

Perl

TCL

Python

Makefile

Education

Bachelor's degree

Master's degree

PhD

Tools

Synopsys TCM/Primetime

Synopsys Fusion/ Design Compiler

Tessent DFT

Job description

Cisco Systems, Inc. in the United States is seeking an ASIC DFT STA Technical Lead.

You will be a detail-oriented STA engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups and exceptions, collaborating with cross-functional teams across design and verification to drive efficient timing closure. You will lead DFT and quality processes through the full implementation flow and post-silicon validation, with exposure to physical design signoff