Hybrid ASIC DFT Engineer for SoC Test & Automation

020 Cisco Systems, Inc.; San Jose (CA); Hybrid; USD 155,000 - 223,000; Full time

Job summary

Cisco Systems, Inc. in San Jose, CA is seeking a Design-for-Testability (DFT) Engineer to support ASIC/SoC DFT implementation, validation, and signoff. You will work with RTL, verification, and test teams to ensure high-quality test coverage and manufacturability.

This hybrid role allows three days per week on-site at our San Jose office. Ideal candidates have hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, and scripting to automate DFT flows.

Qualifications

• Minimum Qualifications: Bachelors + 5 years of related experience, or Master +3 years, or PhD + 0 years, or equivalent.
• Experience with ASIC DFT implementation or validation.
• Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test‑mode controls.
• Experience with stuck‑at and transition fault models.
• Experience with debug DFT rule violations, scan‑chain issues, ATPG coverage gaps, and pattern simulation failures.
• Scripting experience using Tcl, Python, Perl, or shell.

Responsibilities

• Support DFT implementation for ASIC/SoC blocks and subsystems.
• Implement and validate scan insertion, scan compression, OCC, MBIST, boundary scan, and related DFT logic.
• Run DFT rule checks and debug scan, clock, reset, and test‑mode issues.
• Generate and validate ATPG patterns for stuck‑at, transition, and other required fault models.
• Analyze test coverage, pattern count, compression results, and ATPG reports.
• Debug DFT DRC violations, ATPG coverage holes, chain failures, and pattern simulation issues.
• Work with RTL and verification teams to ensure DFT requirements are correctly implemented.
• Support block‑level and full‑chip DFT integration activities.
• Assist with hierarchical DFT flows, pattern retargeting, and validation where applicable.
• Develop and maintain Tcl, Python, Perl, or shell scripts to automate DFT flows and reporting.
• Support silicon debug, diagnosis analysis, and yield‑learning activities as needed.
• Document DFT implementation results, known issues, waivers, and signoff status.

Skills

ASIC DFT implementation

ATPG

MBIST

Scripting (Tcl/Python)

Education

Bachelor's degree or higher in related field

Tools

Siemens Tessent

Synopsys DFT Compiler

TestMAX

Job description

Cisco Systems, Inc. in San Jose, CA is seeking a Design-for-Testability (DFT) Engineer to support ASIC/SoC DFT implementation, validation, and signoff. You will work with RTL, verification, and test teams to ensure high-quality test coverage and manufacturability.

This hybrid role allows three days per week on-site at our San Jose office. Ideal candidates have hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, and scripting to automate DFT flows.