ASIC DFT Engineer

Broadcom; San Jose (CA); Vor Ort; USD 144.000 - 230.000; Vollzeit

Zusammenfassung

Broadcom's ASIC Product Division seeks an ASIC DFT Engineer for our San Jose, California Development Center. The role covers SoC DFT implementation, verification, and debug, including post-silicon bring up.

The candidate will drive test insertion, pattern generation, coverage, and silicon debug while collaborating with cross-functional teams. Strong TCL/Python/C/C++ scripting and Verilog skills are expected.

Qualifikationen

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field with 14+ years of experience.
• Strong DFT and testability experience across ASIC/SoC flows.
• Experience with scanning, BIST, ATPG and related DFT technologies.

Aufgaben

• Define DFT specifications from customer and design requirements across ASICs.
• Implement DFT features including Scan, MBIST, TAP, LBIST, IO, SerDes integration.
• Collaborate with Physical Design and STA teams for design closure.
• Generate, verify and debug Test vectors prior to tape-out.
• Validate and debug Test vectors on ATE during silicon bring-up.
• Assist silicon failure analysis and yield improvement efforts.
• Interface with customers, PD and test teams globally.
• Develop newer DFT solutions and automate flows.

Kenntnisse

DFT background

Scan insertion

ATPG vectors

Verilog coding

Memory BIST

Analog/digital design

Test automation

C++

ATE experience

Ausbildung

Electrical/Computer Engineering degree (14+ yrs)

Tools

TetraMax

Fastscan

DFT Compiler

Mentor TestKompress

Jobbeschreibung

ASIC DFT Engineer

Broadcom's ASIC Product Division is seeking candidates for a DFT Engineer position at our San Jose, California Development Center. The successful candidate will participate in SoC DFT implementation, verification, and debug activities including post-silicon bring up.

Job Description

ASIC DFT Engineer

Broadcom's ASIC Product Division is seeking candidates for a DFT Engineer position at our San Jose, California Development Center. The successful candidate will participate in SoC DFT implementation, verification, and debug activities including post-silicon bring up.

The candidate will support various phases of SoC DFT-related activities for Broadcom APD’s designs, including test insertion, pattern generation, coverage improvement, and basic silicon debug. The role involves collaborating with cross-functional teams, including Physical Design and STA engineers.

Basic coding/scripting skills in TCL, Perl, Python, C++, or Verilog are expected.

Responsibilities

• Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
• Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
• Working closely with STA and DI Engineers design closure for test
• Generating, Verifying & Debugging Test vectors before tape release.
• Validating & Debugging Test vectors on ATE during the silicon bring up phase
• Assisting with silicon failure analysis, diagnostics & yield improvement efforts
• Interfacing with the customer, physical design and test engineering/manufacturing teams located globally
• Working closely with I/P DFT engineers & other stakeholders
• Debugging customer returned parts on the ATE
• Innovating newer DFT solutions to solve testability problems in 3nm & beyond
• Automating DFT & Test Vector Generation flows

Skills/Experience

• Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
• Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
• Logic BIST design and debug experience
• Well-versed in ATPG vector generation, simulation, debug. (TetraMax, Fastscan)
• Experience in Verilog coding, testbench generation & simulation
• Memory BIST insertion and verification experience (SRAM, CAM, eDRAM)
• The ability to work in a multi-disciplined, cross-department environment Solid knowledge in analog and digital circuit design, and device physics fundamentals Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
• Excellent problem solving, debug , root cause analysis and communication skills
• Experience working on ATE is a plus

Education & Experience

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with 14+ years of experience.

Compensation And Benefits

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

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