Senior ASIC DFT Engineer – Next-Gen Networking Chips

Cisco Systems, Inc; Austin (TX); Presencial; USD 149 000 - 251 000; Tempo integral

Resumo da oferta

Cisco Systems, Inc. in Austin, TX is seeking an experienced ASIC DFT Engineer to join the Silicon One development organization. You will collaborate with Front-end RTL and backend PD teams to implement DFT and testability features across the full flow from RTL to post-silicon validation.

The role requires strong background in JTAG, BIST, ATPG, EDA tools, and post-silicon validation with minimal mentorship. You will help craft innovative DFT IP and support test integration for next-generation

Qualificações

• Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 7 years of experience.
• Prior experience working in the latest innovative trends in DFT, test and silicon engineering.
• Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Prior experience working with Gate level simulation, debugging with VCS and other simulators.
• Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687

Responsabilidades

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Conhecimentos

JTAG

BIST

ATPG

Boundary scan

Memory BIST

Gate-level sim

DFT concepts

Formação académica

Bachelor’s or Master’s in Electrical or Computer Engineering

Ferramentas

TestMax

Tetramax

Tessent

PrimeTime

VCS

Descrição da oferta de emprego

Cisco Systems, Inc. in Austin, TX is seeking an experienced ASIC DFT Engineer to join the Silicon One development organization. You will collaborate with Front-end RTL and backend PD teams to implement DFT and testability features across the full flow from RTL to post-silicon validation.

The role requires strong background in JTAG, BIST, ATPG, EDA tools, and post-silicon validation with minimal mentorship. You will help craft innovative DFT IP and support test integration for next-generation