Senior ASIC DFT Engineer - Front/Back-end Validation

Cisco Systems, Inc; San Jose (CA); On-site; USD 170,000 - 290,000; Full time

Job summary

Cisco Systems, Inc. in San Jose seeks a senior engineer to drive DFT and test activities for next-generation networking chips. You will collaborate with Front-end RTL and backend physical design teams to shape silicon architecture and quality processes throughout the implementation flow.

The role emphasizes post-silicon validation, ATPG/EDA tooling, and integration of Verilog-based DFT logic with IP. Strong experience in JTAG, BIST, and door-to-door debug is essential, with opportunities to

Qualifications

• Bachelor's or Master's in Electrical or Computer Engineering with at least 7 years of experience.
• Experience with DFT, test and silicon engineering trends.
• Experience with JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent, PrimeTime.
• Experience with Gate level simulation, debugging with VCS and other simulators.
• Post-silicon validation and debug; able to work with ATE patterns, P1687.

Responsibilities

• Collaborate with Front-end RTL and backend physical design teams to understand chip architecture and drive DFT early in the design cycle.
• Lead DFT and quality processes through the Implementation flow and post-silicon validation phases.
• Gain exposure to physical design signoff activities.

Skills

DFT knowledge

JTAG & BIST understanding

ATPG & EDA tools

Gate level simulation

Post-silicon validation

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

TestMax

Tetramax

Tessent

PrimeTime

VCS

Job description

Cisco Systems, Inc. in San Jose seeks a senior engineer to drive DFT and test activities for next-generation networking chips. You will collaborate with Front-end RTL and backend physical design teams to shape silicon architecture and quality processes throughout the implementation flow.

The role emphasizes post-silicon validation, ATPG/EDA tooling, and integration of Verilog-based DFT logic with IP. Strong experience in JTAG, BIST, and door-to-door debug is essential, with opportunities to