Senior ASIC DFT Engineering Lead

Cisco Systems, Inc.; San Jose (CA); On-site; USD 187,000 - 268,000; Full time

Job summary

Cisco Systems, Inc. is seeking an ASIC Implementation Technical Lead focused on Design-for-Test (DFT) within the Silicon One group.

You will collaborate with Front-end RTL and Backend physical design teams to define DFT requirements early in the design cycle and contribute to post-silicon validation. You will lead the DFT and quality processes across the Implementation flow, work with ATE engineers on pattern translation, and help shape next‑generation networking chips in a fast‑paced, global

Qualifications

• Bachelor's degree in Electrical or Computer Engineering with 8+ years experience, or Master's with 6+ years, or PhD with 3+ years.
• Experience with ATPG and EDA tools like TestMax/Tetramax/Tessent.
• Experience with gate-level simulation and timing-based simulations with SDF, debugging with VCS.
• Post-silicon validation and debug experience.
• Experience with scan insertion.

Responsibilities

• Collaborate with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.
• Involved in crafting groundbreaking next-generation networking chips.
• Lead to drive the DFT and quality process through the entire Implementation flow and post-silicon validation phases with exposure to physical design signoff activities.
• Collaborate with ATE engineers on pattern translation and validation.

Skills

DFT experience

ATPG

Gate-level simulation

Post-silicon validation

Scan insertion

Verilog design

JTAG protocols (p1500, p1687)

Scripting (Tcl, Python/Perl)

SSN

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

TestMax

Tetramax

Tessent

Job description

Cisco Systems, Inc. is seeking an ASIC Implementation Technical Lead focused on Design-for-Test (DFT) within the Silicon One group.

You will collaborate with Front-end RTL and Backend physical design teams to define DFT requirements early in the design cycle and contribute to post-silicon validation. You will lead the DFT and quality processes across the Implementation flow, work with ATE engineers on pattern translation, and help shape next‑generation networking chips in a fast‑paced, global