ASIC DFT/STA Engineer – Next-Gen Networking Silicon

Cisco Systems, Inc.; San Jose (CA); On-site; USD 168,000 - 245,000; Full time

Benefits offered by this job

Medical insurance

Dental and vision insurance

401(k) plan with company matching

Job summary

Cisco Silicon One is seeking an ASIC DFT STA Engineer to join the team that designs silicon platforms powering AI-era networking. You will drive timing constraints, STA, and DFT through the full flow from RTL to post-silicon validation, collaborating with cross‑functional teams to push boundaries and deliver high-quality silicon.

The role requires strong analytical skills, experience with timing closure and tools like Synopsys TCM/Primetime, and a track record in DFT methodologies.

Qualifications

• Bachelor's or higher with several years in RTL/CDC/RDC and SDC development.
• Experience in timing constraint development and verification.
• Proficiency in at least two scripting languages: Perl, TCL, Python or Makefile.

Responsibilities

• Lead DFT/STA efforts across the implementation flow and post-silicon validation.
• Collaborate with cross-functional teams to optimize timing and quality.
• Support hardware platform timing closure including scan, BIST, and related X-checks.

Skills

RTL design

CDC/RDC

SDC development

Timing constraints

Scripting languages

Education

Bachelor's + 7 years

Master's + 4 years

PhD + 1 year

Tools

Synopsys Fusion/Design Compiler

Primetime/TCM

Tessent

Job description

Cisco Silicon One is seeking an ASIC DFT STA Engineer to join the team that designs silicon platforms powering AI-era networking. You will drive timing constraints, STA, and DFT through the full flow from RTL to post-silicon validation, collaborating with cross‑functional teams to push boundaries and deliver high-quality silicon.

The role requires strong analytical skills, experience with timing closure and tools like Synopsys TCM/Primetime, and a track record in DFT methodologies.