Senior ASIC DFT/DV Engineer – Hybrid

Cisco Systems, Inc.; San Jose (CA); Hybrid; USD 168,000 - 245,000; Full time

Job summary

Cisco Systems, Inc. in the United States is seeking a senior test engineer to lead DFT test planning and testbench development for advanced silicon devices. You will collaborate across design, verification and PD teams to integrate test logic through all stages from design to post-silicon validation.

The role requires strong SystemVerilog expertise, DVE/Verdi debugging, and scripting with TCL and Python. This is a hybrid position with locations in San Jose or Austin.

Qualifications

• Bachelor's in Electrical Engineering or equivalent with 7+ years (or Master's with 4+ years) of experience.
• Experience in test planning based on complex design specifications.
• Experience in testbench development using SystemVerilog.

Responsibilities

• Thorough test planning and development of test benches to verify DFT architecture for ATE screening, in-system test, debug and diagnostics needs.
• Collaborate with design/verification and PD teams to enable integration and validation of test logic in all phases.
• Work on innovative hardware DFT & test strategy for new silicon device models, bare die & stacked die, driving reusable test and debug methodologies.

Skills

Test planning

Testbench development

SystemVerilog

DVE/Verdi

TCL

Python

Education

Bachelor's in Electrical Engineering or equivalent

Master's in Electrical Engineering

Tools

DVE/Verdi

SystemVerilog

Job description

Cisco Systems, Inc. in the United States is seeking a senior test engineer to lead DFT test planning and testbench development for advanced silicon devices. You will collaborate across design, verification and PD teams to integrate test logic through all stages from design to post-silicon validation.

The role requires strong SystemVerilog expertise, DVE/Verdi debugging, and scripting with TCL and Python. This is a hybrid position with locations in San Jose or Austin.