ASIC DFT Engineer – Test & Post‑Silicon Validation

Cisco; San Jose (CA); On-site; USD 155,000 - 223,000; Full time

Job summary

Cisco's Silicon One team is seeking an ASIC Engineer focused on Design-for-Test. You will collaborate with Front-end RTL and backend physical design to drive DFT requirements early in the design cycle as we craft next-generation networking chips.

The role emphasizes post-silicon validation, ATE patterns, and verifying testability across the Implementation flow, with opportunities to influence DFT strategies and quality processes.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering with 3+ years of experience.
• Experience with DFT, test and silicon engineering.
• Experience with JTAG, Scan and BIST architectures.

Responsibilities

• Design-for-Test focus working with Front-end RTL and backend physical design teams.
• Drive DFT requirements early in the design cycle and guide post-silicon validation.

Skills

DFT expertise

JTAG protocols

Scan and BIST

ATPG

Gate level simulation

Post-silicon validation

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

TestMax

Tetramax

Tessent

PrimeTime

VCS

Job description

Cisco's Silicon One team is seeking an ASIC Engineer focused on Design-for-Test. You will collaborate with Front-end RTL and backend physical design to drive DFT requirements early in the design cycle as we craft next-generation networking chips.

The role emphasizes post-silicon validation, ATE patterns, and verifying testability across the Implementation flow, with opportunities to influence DFT strategies and quality processes.