Senior ASIC DFT & DV Engineer (DVE/Verdi)

Cisco; Austin (TX); Hybrid; USD 168,000 - 245,000; Full time

Benefits offered by this job

Medical, dental & vision insurance

401(k) with Cisco matching

Paid parental leave

Paid holidays

Job summary

Cisco’s Silicon One team seeks an experienced hardware test engineer to lead test planning and bench development for Design-for-Test architecture. You will collaborate across design, verification, and PD teams to validate test logic and enable robust in-system testing through post-silicon validation.

The role requires strong SystemVerilog skills, DVE/Verdi debugging, and scripting in TCL/Python/Perl, with 7+ years of experience (or 4+ if MS) in EE. Hybrid role across San Jose or Austin.

Qualifications

• Bachelor’s in Electrical Engineering or equivalent with 7+ years (or Master’s with 4+ years).
• Experience in test planning based on complex design specs.
• Experience in testbench development using SystemVerilog.
• Experience debugging using DVE/Verdi.
• Experience with TCL, Python or Perl.

Responsibilities

• Develop and implement thorough test plans and test benches for DFT architecture supporting ATE screening, in-system test, debug and diagnostics.
• Collaborate with design, design- verification and PD teams to validate test logic across implementation and post-silicon validation flows.
• Contribute to hardware DFT and test strategy for new silicon device models, bare die & stacked die, driving reusable test and debug methodologies.

Skills

Test planning

Testbench development

Debugging (DVE/Verdi)

Scripting (TCL/Python/Perl)

Education

Bachelor’s in Electrical Engineering

Master’s (preferred)

Tools

SystemVerilog

DVE/Verdi

Job description

Cisco’s Silicon One team seeks an experienced hardware test engineer to lead test planning and bench development for Design-for-Test architecture. You will collaborate across design, verification, and PD teams to validate test logic and enable robust in-system testing through post-silicon validation.

The role requires strong SystemVerilog skills, DVE/Verdi debugging, and scripting in TCL/Python/Perl, with 7+ years of experience (or 4+ if MS) in EE. Hybrid role across San Jose or Austin.