Senior ASIC DFT and Memory Validation Engineer

Cisco; San Jose (CA); Hybrid; USD 168.000 - 245.000; Vollzeit

Benefits dieser Stelle

Health insurance

401(k) matching

Paid holidays

Birthday leave

Wellness days

Stock grants

Flexible vacation

Sick leave

Zusammenfassung

Cisco's Silicon One team in San Jose seeks an experienced engineer to lead test planning and DFT verification for next‑gen silicon. You will develop test benches and own MBIST methodology across the portfolio, collaborating with RTL and physical design teams to ensure high‑quality verification and scalable infrastructure.

Ideal candidates have 7+ years in test planning and deep familiarity with memory architectures and DFT tools (DVE/Verdi, DesignWare, Tessent).

Qualifikationen

• Bachelor's in Electrical Engineering or equivalent required.
• 7+ years of test planning experience, or 4+ years with a Master's.
• Experience with memory architectures (SRAM/DRAM) and failure modes.

Aufgaben

• Plan tests and develop test benches for DFT verification.
• Own MBIST methodology across the Silicon One portfolio.

Kenntnisse

Test planning

MBIST

DFT architecture

Verilog/SV

DVE/Verdi

Python/TCL

Memory architectures

Debugging

Ausbildung

Bachelor's in Electrical Engineering or equivalent

Master's in Electrical Engineering

Tools

DVE/Verdi

Synopsys DesignWare

SMS

TestMax

Mentor Tessent

Jobbeschreibung

Cisco's Silicon One team in San Jose seeks an experienced engineer to lead test planning and DFT verification for next‑gen silicon. You will develop test benches and own MBIST methodology across the portfolio, collaborating with RTL and physical design teams to ensure high‑quality verification and scalable infrastructure.

Ideal candidates have 7+ years in test planning and deep familiarity with memory architectures and DFT tools (DVE/Verdi, DesignWare, Tessent).