ASIC DFT Verification Lead - Hybrid San Jose

Cisco; San Jose (CA); Hybrid; USD 187,000 - 268,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid parental leave

Disability coverage

Cisco restricted stock units

Job summary

The Silicon One team at Cisco is seeking a DFT Verification Lead in San Jose, CA. You will own test planning and develop test benches to verify DFT architecture for ATE screening, in-system test, and debug needs.

You will collaborate across front-end RTL, back-end physical design, and PD teams to validate tests in all design phases and post-silicon flows. Ideal candidates bring 8+ years of related experience or 6+ years with a Master's, and strong SystemVerilog and DVE/Verdi debugging skills.

Qualifications

• Bachelor's degree plus 8 years of related experience or Master's 6 years or PhD 3 years.
• Experience in test planning based on complex design specifications.
• Experience in testbench development using SystemVerilog.
• Experience debugging using DVE/Verdi.
• Experience with TCL, Python or Perl.

Responsibilities

• Responsible for thorough test planning and development of test benches to verify DFT architecture supporting ATE screening and in-system test.
• Collaborate with design/verification and PD teams to integrate test logic in all phases of implementation and post-silicon validation.
• Drive innovative hardware DFT and test strategy for new silicon device models and stacked die, promoting reusable test methods.
• Craft solutions and debug with minimal mentorship as a DFT Verification Lead in San Jose, collaborating with RTL and backend teams.

Skills

SystemVerilog

DVE/Verdi

TCL

Python

Debugging

Education

Bachelor's degree in related field

Master's degree in related field

PhD in related field

Tools

DVE/Verdi

Job description

The Silicon One team at Cisco is seeking a DFT Verification Lead in San Jose, CA. You will own test planning and develop test benches to verify DFT architecture for ATE screening, in-system test, and debug needs.

You will collaborate across front-end RTL, back-end physical design, and PD teams to validate tests in all design phases and post-silicon flows. Ideal candidates bring 8+ years of related experience or 6+ years with a Master's, and strong SystemVerilog and DVE/Verdi debugging skills.