Senior ASIC DFT & DV Engineer - Hybrid (San Jose/Austin)

020 Cisco Systems, Inc.

San Jose (CA)

Hybrid

USD 168.000 - 245.000

Vollzeit

Vor 2 Tagen
Sei unter den ersten Bewerbenden

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Zusammenfassung

Cisco Systems, Inc. is seeking an experienced engineer to lead test planning and design-for-test development for advanced silicon platforms. You will craft test benches, verify DFT architectures, and collaborate with design and PD teams to implement robust in-system test and debug flows.

The role emphasizes reusable test methods for new silicon models, bare die, and stacked die, with a focus on efficient debugging and cross‑functional collaboration in a hybrid work setting.

Qualifikationen

  • Bachelor's in Electrical Engineering or equivalent with 7+ years (or Master's with 4+ years) of experience
  • Experience in test planning based on complex design specifications
  • Testbench development using System Verilog
  • Debugging using DVE/Verdi
  • Experience with TCL, Python or Perl

Aufgaben

  • Develop test benches and verify comprehensive DFT architecture for ATE screening, in-system test, debugging and diagnostics
  • Collaborate with design/verification and PD teams to enable integration and validation of test logic in all phases of implementation
  • Contribute to hardware DFT & test strategy for new silicon device models, bare die & stacked die
  • Craft solutions and debug efficiently

Kenntnisse

Test planning
Test bench debugging
Collaboration
DVE/Verdi debugging
TCL/Python/Perl scripting

Ausbildung

Bachelor's in Electrical Engineering or equivalent
Master's in Electrical Engineering or related field

Tools

SystemVerilog
DVE/Verdi
UVM

Jobbeschreibung

Cisco Systems, Inc. is seeking an experienced engineer to lead test planning and design-for-test development for advanced silicon platforms. You will craft test benches, verify DFT architectures, and collaborate with design and PD teams to implement robust in-system test and debug flows.

The role emphasizes reusable test methods for new silicon models, bare die, and stacked die, with a focus on efficient debugging and cross‑functional collaboration in a hybrid work setting.

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