Innovative ASIC DFT Engineer - Design for Test

Cisco Systems, Inc.; San Jose (CA); On-site; USD 120,000 - 190,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid parental leave

Disability insurance

Life insurance

Job summary

Cisco Systems, Inc. is seeking an ASIC Design for Test Engineer within the Silicon One team.

You will drive Design-for-Test features for ATE, in-system test, and diagnostics, collaborating with frontend RTL and backend Physical Design to thread DFT requirements early in the design cycle. The role uses SystemVerilog for validation, and ATPG/EDA tools such as TestMax, Tetramax, Tessent, and PrimeTime to generate and analyze test patterns.

Qualifications

• Meet one of the following (completed within the past 3 years or expected to be completed within the next 12 months):
• Master's degree with 0 years of work experience; or
• Bachelor's degree with 2 years of work experience.
• Qualifying education and work experience should be in ASIC Engineering or a related field.
• Foundational understanding or academic/internship exposure to JTAG protocols, scan architectures, and BIST (Built-In Self-Test, including memory BIST and boundary scan).
• Familiarity or introductory hands-on exposure to EDA and ATPG tools along with scripting or coding skills in Python, Tcl, or Perl.
• Experience working with gate-level simulations and debugging using simulators like VCS.

Responsibilities

• Implement the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs.
• Create and enhance automation scripts to improve implementation robustness and efficiency.
• Work closely with the Design, Design Verification, and Physical Design teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Collaborate with team members to validate test timing and logic equivalency of designs using SystemVerilog.
• Utilize ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime) for test pattern generation and analysis.

Skills

JTAG protocols

Scan architectures

BIST

Python scripting

SystemVerilog

Education

Master's degree in ASIC Engineering

Bachelor's degree in related field

Tools

TestMax

Tetramax

Tessent

PrimeTime

Job description

Cisco Systems, Inc. is seeking an ASIC Design for Test Engineer within the Silicon One team.

You will drive Design-for-Test features for ATE, in-system test, and diagnostics, collaborating with frontend RTL and backend Physical Design to thread DFT requirements early in the design cycle. The role uses SystemVerilog for validation, and ATPG/EDA tools such as TestMax, Tetramax, Tessent, and PrimeTime to generate and analyze test patterns.