Senior ASIC Design Verification Engineer

Meta; Menlo Park (CA); On-site; USD 146,000 - 209,000; Full time

Job summary

Meta is seeking an ASIC Design Verification Engineer to join the Infrastructure organization in Menlo Park, CA. You will verify IP and SoC designs for data center applications, building UVM-based test benches and using Formal and Emulation approaches to achieve bug-free silicon.

You will work with cross-functional teams across Design, Model, Emulation, and Silicon Validation, driving verification closure and continuous improvement with the latest methodologies and tools.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or related technical field.
• Hands-on experience with SystemVerilog/UVM and C/C++ verification.
• Proficient in scripting (Python, TCL, Perl, Shell).
• Experience with version control systems (Mercurial, Git, SVN).

Responsibilities

• Define and implement IP/SoC verification plans and build verification test benches.
• Develop functional tests based on verification plans and drive closure with coverage metrics.
• Debug root-cause and resolve functional failures with Design team.
• Collaborate with cross-functional teams including Design, Model, Emulation and Silicon validation.

Skills

SystemVerilog/UVM

C/C++ verification

Python

TCL

Perl

Shell scripting

Mercurial

Git

SVN

Education

Bachelor's degree in CS/CE or related field

Tools

UVM methodology

Job description

Meta is seeking an ASIC Design Verification Engineer to join the Infrastructure organization in Menlo Park, CA. You will verify IP and SoC designs for data center applications, building UVM-based test benches and using Formal and Emulation approaches to achieve bug-free silicon.

You will work with cross-functional teams across Design, Model, Emulation, and Silicon Validation, driving verification closure and continuous improvement with the latest methodologies and tools.