ASIC Engineer, Design Verification

Meta; Menlo Park (CA); On-site; USD 146,000 - 209,000; Full time

Job summary

Meta is seeking an ASIC Design Verification Engineer to join the Infrastructure organization in Menlo Park, CA. You will verify IP and SoC designs for data center applications, building UVM-based test benches and using Formal and Emulation approaches to achieve bug-free silicon.

You will work with cross-functional teams across Design, Model, Emulation, and Silicon Validation, driving verification closure and continuous improvement with the latest methodologies and tools.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or related technical field.
• Hands-on experience with SystemVerilog/UVM and C/C++ verification.
• Proficient in scripting (Python, TCL, Perl, Shell).
• Experience with version control systems (Mercurial, Git, SVN).

Responsibilities

• Define and implement IP/SoC verification plans and build verification test benches.
• Develop functional tests based on verification plans and drive closure with coverage metrics.
• Debug root-cause and resolve functional failures with Design team.
• Collaborate with cross-functional teams including Design, Model, Emulation and Silicon validation.

Skills

SystemVerilog/UVM

C/C++ verification

Python

TCL

Perl

Shell scripting

Mercurial

Git

SVN

Education

Bachelor's degree in CS/CE or related field

Tools

UVM methodology

Job description

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of an agile team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.ASIC Engineer, Design Verification Responsibilities:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verificationDevelop functional tests based on verification test planDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverageDebug, root-cause and resolve functional failures in the design, partnering with the Design teamCollaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification and coverage goalsDevelop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industryMinimum Qualifications:Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologiesExperience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environmentsPreferred Qualifications:Experience working across and building relationships with cross-functional design, model and emulation teamsExperience with revision control systems like Mercurial(Hg), Git or SVNExperience in architecting and implementing Design Verification infrastructure and executing the full verification cycleExperience with Design verification of Data-center applications like Video, AI/ML and Networking designsTrack record of 'first-pass success' in ASIC development cyclesExperience with micro-architectural performance verificationExperience verifying GPU/CPU designsExperience with verification of ARM/RISC-V based sub-systems or SoCsExperience in development of UVM based verification environments from scratchExperience with IP or integration verification of high-speed interfaces like PCIe, RoCE, DDR, HBM, EthernetExperience in one or more of the following areas along with functional verification - SV Assertions, Formal, EmulationAbout Meta:Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].$146,000/year to $209,000/year + bonus + equity + benefitsIndividual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.