ASIC Verification Engineer

Links Technology Solutions, Inc.; Carlsbad (CA); On-site; USD 96,000 - 110,000; Full time

Benefits offered by this job

Health insurance

Life insurance

Vision insurance

Dental insurance

401K Matching

Job summary

Links Technology Solutions, Inc. in Carlsbad, CA onsite/hybrid is seeking an ASIC Verification Engineer with 5-12 years of experience to join our team and contribute to next-generation SoC designs.

You will develop UVM-based verification environments and participate in architectural decisions that impact silicon quality and delivery timelines. Collaboration with architecture, design, and firmware teams will be essential as you create test plans, assertions, scoreboards, and debugging tools to

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• Experience with UVM-based testbench development and verification across block to system levels.
• Proficiency in SystemVerilog and familiarity with verification methodologies.
• Experience in ASIC or SoC verification and testplan development.
• Scripting skills with Python or Perl for automation.
• Familiarity with high-speed serial protocols (PCIe/UCIe) and analog debugging.

Responsibilities

• Develop and implement UVM-based verification environments.
• Create comprehensive verification plans at block and system levels.
• Design verification components including assertions, traffic generators, agents, and scoreboards.
• Collaborate with cross-functional teams to evaluate design testability and verification requirements.
• Lead debug efforts and provide solutions for complex technical challenges.

Skills

UVM testbench development

SystemVerilog

Debug complex designs

Python or Perl scripting

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical/Communications Engineering or related field

Tools

SystemVerilog

C programming

Python

PCIe/UCIe protocols

Job description

Title: ASIC VERIFICATION ENGINEER

Location: Carlsbad, CA onsite/hybrid

Pay Rate: $70-$80/HR

Duration:1 yr extendable

Summary: Join our client's innovative team developing next-generation silicon solutions for a major network manufacturer. We are seeking a collaborative Design Verification Engineer with 5-12 years of industry experience to help create cutting edge System-on-Chip (SoC) designs delivered first time right. You will work in a collaborative environment, participating in architectural decisions and verification strategies that directly impact product success. Our team values diverse perspectives and creative problem-solving approaches to deliver exceptional customer experiences.

Description – ASIC Verification Engineer

• Develop and implement Universal Verification Methodology (UVM) based verification environments.
• Create comprehensive verification plans at both block and system levels.
• Design and implement verification components including assertions, traffic generators, agents, and scoreboards.
• Collaborate with cross-functional teams to evaluate design testability and verification requirements.
• Lead debug efforts and provide solutions for complex technical challenges.

Qualifications – ASIC Verification Engineer

• Bachelor's degree in Electrical Engineering or a related field.
• UVM Based testbench development.
• Experience in ASIC or SOC verification.
• Demonstrated experience in developing test plans and verification infrastructure.
• Practical knowledge of verification methodologies from block level to system level.
• Proficiency in System Verilog.
• Experience in identifying and resolving complex design and verification issues.
• Timing and gate level simulation experience.
• C coding for firmware delivery for post silicon bringup.
• Bachelors/master's degree in electrical or communications engineering or a related field.
• Experience with formal verification techniques including abstraction and end-to-end checking.
• Experience with industry-standard tools and scripting languages (Python or Perl) for automation.
• System Verilog coding and debug.
• AI based CAD efficiency improvisation initiatives.
• High speed serial protocols preferred UCIe, PCIE.
• Analog debug experience including DAC/ADC & calibrations white-box verification.

Benefits:

• $70-$80/hr
• Available health, life, vision, and dental insurance
• 401K Matching