Staff ASIC Verification Engineer

ScaleFlux; Milpitas (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

ScaleFlux is seeking ASIC verification engineers for its team in Milpitas, California. The role involves collaboration with design teams, defining test plans, and developing verification environments. The ideal candidate is proficient in UVM methodology and has strong debugging skills.

If you are passionate about creating innovative technologies in a fast-paced environment, we encourage you to apply. Join us in shaping the future of cloud and data center infrastructure!

Qualifications

• BSEE, MSEE or above is required.
• Proficient in UVM methodology and verification development.
• Strong experience with debug tools and simulation environments.

Responsibilities

• Work closely with the design team on specifications and architectures.
• Define test plans and develop verification environments.
• Produce functional and code coverage metrics and debug issues.

Skills

Proficiency in UVM methodology

Constrained Random

Coverage Driven Methodology

Verilog

System Verilog

Debug skills

Education

BSEE, MSEE or above

Tools

Verilog simulator

Debug tools (e.g., Verdi)

Job description

We are looking for ASIC verification engineers to join our rapidly growing engineering team focused on breakthrough cloud and data center infrastructure solutions involving both storage and computing.

The ideal candidate for this role shares our passion for creating innovative technologies, and thrives in a highly dynamic, fast-paced, results-driven environment. We are looking for highly talented, passionate, and versatile engineers that can create next generation enterprise data center solutions.

Location: Milpitas, California

Responsibilities

• Work closely with the design team to review and understand specifications / architectures / micro-architectures
• Define test plans
• Develop block level and chip level verification environments
• Produce functional / code coverage metrics
• Run regression and debug / triage failures in simulation environment
• Validate features and work with software teams to debug issues in the lab

Qualifications

• BSEE, MSEE or above
• Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, System Verilog and test development for verification
• Good knowledges of Verilog simulator and waveform viewer
• Strong debug skills and experience with debug tools, such as Verdi