Staff ASIC Verification Architect (SoC/IP) – UVM Expert

Meta; Sunnyvale (CA); On-site; USD 178,000 - 250,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification Engineer to lead the verification strategy for custom silicon that powers Meta's data centers. You will architect verification environments and partner with teams to ensure first-pass silicon success.

The ideal candidate should have 8+ years of experience in SystemVerilog/UVM methodology, solid knowledge of EDA tools, and a proven track record in verifying complex systems.

Qualifications

• 8+ years of hands-on experience in SystemVerilog/UVM methodology.
• Experience in IP/sub-system and/or SoC level verification.
• Familiarity with SV Assertions, Formal, and Emulation.

Responsibilities

• Define and implement IP/SoC verification plans.
• Develop functional tests based on verification test plan.
• Collaborate with cross-functional teams to improve design quality.

Skills

SystemVerilog/UVM

C/C++ programming

EDA tools

Python

TCL

Shell scripting

Education

Bachelor's degree in Computer Science or Engineering

Tools

UVM-based verification environments

Job description

Meta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification Engineer to lead the verification strategy for custom silicon that powers Meta's data centers. You will architect verification environments and partner with teams to ensure first-pass silicon success.

The ideal candidate should have 8+ years of experience in SystemVerilog/UVM methodology, solid knowledge of EDA tools, and a proven track record in verifying complex systems.