Senior ASIC Validation & Emulation Engineer

Meta

Menlo Park (CA)

On-site

USD 146,000 - 209,000

Full time

4 days ago
Be an early applicant
Application generator

Stand out for this role — generate a tailored resume and cover letter in about a minute.

Get past ATS filters

Job summary

Meta's Infrastructure Silicon organization seeks an experienced Silicon Validation Engineer to join our team in Menlo Park. You will work across the full silicon lifecycle, from pre-silicon design input and FPGA emulation to post-silicon bring-up and deployment in production fleets.

You will define validation strategies and drive emulation bring-up. The role requires hands-on experience with RTL, emulation platforms, and software tooling; you will build automation, debug complex

Qualifications

  • Requires 6+ years in ASIC/SoC development cycles with pre-silicon and/or post-silicon validation.
  • Experience debugging hardware–software interactions using waveform viewers, logic analyzers, and hardware debug probes.
  • Proficiency in Python/C++ automation scripts for validation.
  • Familiar with RTL partitioning, emulation, and post-silicon validation.

Responsibilities

  • Validate silicon across full lifecycle from pre-silicon input to post-silicon fleet deployment.
  • Develop and maintain emulation infrastructure and FPGA-based platforms.
  • Partition RTL onto emulation platforms optimizing timing and debug visibility.
  • Create and maintain automation for validation workflows and diagnostics.
  • Collaborate with RTL design, verification, firmware, software, and systems teams to resolve issues.

Skills

ASIC/SoC verification
Python scripting
FPGA emulation
Debug / troubleshooting
Linux

Education

Bachelor's degree in Computer Science/Engineering or relevant field

Tools

SystemVerilog
UVM
VCS
Xcelium
Questa
Palladium
Veloce
Zebu

Job description

Meta's Infrastructure Silicon organization seeks an experienced Silicon Validation Engineer to join our team in Menlo Park. You will work across the full silicon lifecycle, from pre-silicon design input and FPGA emulation to post-silicon bring-up and deployment in production fleets.

You will define validation strategies and drive emulation bring-up. The role requires hands-on experience with RTL, emulation platforms, and software tooling; you will build automation, debug complex

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Senior Silicon Validation Engineer (Pre/Post‑Silicon)
Senior Silicon Validation Engineer (Pre/Post‑Silicon)

Meta • Sunnyvale (CA)

On-site
USD 146,000 - 209,000
Senior ASIC Design Verification Engineer
Senior ASIC Design Verification Engineer

Meta • Menlo Park (CA)

On-site
USD 146,000 - 209,000
Pre-Silicon Emulation Engineer for ASIC Validation & Automation
Pre-Silicon Emulation Engineer for ASIC Validation & Automation

MetAntz • Sunnyvale (CA)

On-site
USD 140,000 - 190,000
Senior Infra Silicon Validation Lead
Senior Infra Silicon Validation Lead

Meta • Sunnyvale (CA)

On-site
USD 212,000 - 294,000
Bonus
Equity
Benefits
Post-Silicon Emulation Engineer for SoC Validation
Post-Silicon Emulation Engineer for SoC Validation

Qualcomm • San Diego (CA)

Hybrid
USD 99,000 - 148,000
Senior Emulation Architect - Pre-Silicon Validation
Senior Emulation Architect - Pre-Silicon Validation

Astera Labs • San Jose (CA), Northern (KY)

Hybrid
USD 207,000 - 230,000
Discretionary bonus
Competitive benefits
Relocation assistance
Senior Emulation Architect for SoC Validation
Senior Emulation Architect for SoC Validation

Astera Labs • San Jose (CA)

On-site
USD 207,000 - 230,000
Senior ASIC Verification Engineer: Pre-Silicon & Emulation
Senior ASIC Verification Engineer: Pre-Silicon & Emulation

Palo Alto Networks, Inc. • Santa Clara (CA)

On-site
USD 106,000 - 172,000
Hardware Emulation & Validation Engineer (ASIC/FPGA)
Hardware Emulation & Validation Engineer (ASIC/FPGA)

Nutanix • San Diego (CA)

On-site
USD 99,000 - 148,000
Competitive benefits
ASIC Engineer / (Pre/Post) Silicon Validation Engineer
ASIC Engineer / (Pre/Post) Silicon Validation Engineer

Meta • Sunnyvale (CA)

On-site
USD 146,000 - 209,000