Senior ASIC Verification Engineer: Pre-Silicon & Emulation

Palo Alto Networks, Inc.; Santa Clara (CA); On-site; USD 106,000 - 172,000; Full time

Job summary

Palo Alto Networks is seeking a Design Verification engineer for the ASIC team in Santa Clara, CA. You will define verification methodologies, architect test benches, write tests, and debug across simulation, emulation, formal verification, and silicon validation.

Office-based with four days in the office per week and one day remote. Collaborate with software, architecture, and ASIC design teams to deliver pre-silicon verification plans and scalable test benches.

Qualifications

• BS in EE/CE/CS or equivalent experience
• 3+ years in ASIC design verification
• Strong SystemVerilog and UVM
• Experience with coverage models and test benches
• Self-checking infrastructure with reference models and scoreboards

Responsibilities

• Define verification methodologies and test plans
• Architect test benches and write tests across simulation, emulation, formal verification and silicon validation
• Develop flows for emulation and run/debug tests with engineers and ASIC designers
• Create Python tools to automate triage, coverage closure, and metrics-driven verification

Skills

SystemVerilog

UVM

Python

C/C++

Regression testing

Debugging

Test benches

Scoreboards

Education

BS in EE/CE/CS

MSEE preferred

Tools

UNIX shell

Perl

Verilog/VHDL

Job description

Palo Alto Networks is seeking a Design Verification engineer for the ASIC team in Santa Clara, CA. You will define verification methodologies, architect test benches, write tests, and debug across simulation, emulation, formal verification, and silicon validation.

Office-based with four days in the office per week and one day remote. Collaborate with software, architecture, and ASIC design teams to deliver pre-silicon verification plans and scalable test benches.