ASIC Engineer, Design Verification

Meta; Sunnyvale (CA); On-site; USD 178,000 - 250,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification Engineer to lead the verification strategy for custom silicon that powers Meta's data centers. You will architect verification environments and partner with teams to ensure first-pass silicon success.

The ideal candidate should have 8+ years of experience in SystemVerilog/UVM methodology, solid knowledge of EDA tools, and a proven track record in verifying complex systems.

Qualifications

• 8+ years of hands-on experience in SystemVerilog/UVM methodology.
• Experience in IP/sub-system and/or SoC level verification.
• Familiarity with SV Assertions, Formal, and Emulation.

Responsibilities

• Define and implement IP/SoC verification plans.
• Develop functional tests based on verification test plan.
• Collaborate with cross-functional teams to improve design quality.

Skills

SystemVerilog/UVM

C/C++ programming

EDA tools

Python

TCL

Shell scripting

Education

Bachelor's degree in Computer Science or Engineering

Tools

UVM-based verification environments

Job description

Summary

Meta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification Engineer to drive verification strategy and execution for custom silicon powering Meta's data center infrastructure. In this role, you will lead the end-to-end verification of complex IP blocks and SoCs designed for AI/ML acceleration, networking, and video processing workloads. You will architect scalable UVM-based verification environments, define coverage models, and partner with design, emulation, and post-silicon validation teams to achieve first-pass silicon success across Meta's infrastructure ASIC portfolio.

Required Skills

1. Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
2. Develop functional tests based on verification test plan
3. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
4. Debug, root-cause and resolve functional failures in the design, partnering with the Design team
5. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
6. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Minimum Qualifications

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
2. 8+ years of hands‑on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
3. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
4. Experience in one or more of the following areas along with functional verification: SV Assertions, Formal, Emulation
5. Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
6. Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Preferred Qualifications

1. Experience with compute and/or memory subsystem and/or collective functional and performance verification
2. Experience with verification of ARM/RISC-V/GPU based sub-systems or SoCs
3. Experience in development of UVM based verification environments from scratch
4. Prior experience with fullchip or package-level integration projects
5. Experience working across and building relationships with cross-functional design, model and emulation teams
6. Familiarity with host and system-level concepts for functional verification
7. Experience with chiplet based architectures and package-level integration verification

Public Compensation

$178,000/year to $250,000/year + bonus + equity + benefits

Industry

Internet

Equal Opportunity

Meta is proud to be an Equal Employment Opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state, and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].