Senior ASIC Design & Verification Eng - Hybrid Sunnyvale

Salt; San Francisco (CA); Hybride; USD 180 000 - 280 000; Plein temps

Résumé du poste

Salt in Sunnyvale, CA, is seeking an ASIC Design and/or Verification Engineer (Sr. to Principal) to design, verify and optimize high-performance networking chips in a hybrid work model.

You will write Verilog/SystemVerilog, develop specs, mentor juniors, and collaborate with Physical Design to meet timing and power targets.

Candidates have 4–15+ years of relevant experience and a strong background in architecture, verification, and scripting with Perl or Python.

Qualifications

• Bachelor’s degree in Engineering; Master’s strongly desired.
• Experience leading high-performance subsystems from spec to final netlist.
• Knowledge of computer architecture and networking protocols.
• Strong Verilog/SystemVerilog coding skills from prior work.
• Knowledge of synthesis and lint tools used in ASIC flows.
• Excellent written and verbal communication skills.
• Proficiency in Perl/Python.

Responsabilités

• Architect/verify complex modules and subsystems for high-performance chips.
• Write detailed functional and micro-architecture specifications.
• Implement design/verification using Verilog or SystemVerilog.
• Write functional coverage/SVA to catch corner-case bugs.
• Ensure modules meet power targets using advanced power-reduction techniques.
• Work with Physical Design for timing closure and RTL timing fixes.
• Collaborate with Design/Verification to ensure full validation.
• Lead and mentor new graduates and interns.

Connaissances

Verilog/SystemVerilog

Leadership

Python/Perl

Communications

Synthesis/Lint

Formation

Bachelor’s degree in Engineering

Master’s degree strongly desired

Outils

Synthesis tools

Description du poste

Salt in Sunnyvale, CA, is seeking an ASIC Design and/or Verification Engineer (Sr. to Principal) to design, verify and optimize high-performance networking chips in a hybrid work model.

You will write Verilog/SystemVerilog, develop specs, mentor juniors, and collaborate with Physical Design to meet timing and power targets.

Candidates have 4–15+ years of relevant experience and a strong background in architecture, verification, and scripting with Perl or Python.