Hybrid Senior ASIC Engineer - High-Speed Networking

HITEC; Roseville, Northern (CA, KY); Hybrid; USD 140,000 - 230,000; Full time

Job summary

Hewlett Packard Enterprise in California is seeking a Sr. ASIC Design Engineer for a hybrid role requiring on-site ~2 days per week.

You will lead the design of high-speed networking ASICs, from specifications to netlist, with emphasis on Verilog/SystemVerilog, timing closure, and integration with physical design. You will mentor new engineers, collaborate with verification and PD teams, and contribute to architectural decisions.

Qualifications

• Bachelor’s degree in Electrical Engineering required; Master’s strongly desired.
• 5+ years of relevant ASIC design experience preferred.
• Proficiency with Verilog/SystemVerilog and EDA flows.

Responsibilities

• Develop functional specifications and micro-architectures for ASIC modules.
• Implement designs using Verilog or SystemVerilog.
• Create functional coverage and assertions (SVA) for verification.
• Collaborate with Physical Design for floorplanning and timing closure.
• Mentor new engineers and interns.

Skills

Verilog

SystemVerilog

Computer Architecture

Networking protocols

Analytical/problem solving

Leadership/mentoring

Education

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

Tools

Synthesis tools

Lint tools

Timing analysis

Job description

Hewlett Packard Enterprise in California is seeking a Sr. ASIC Design Engineer for a hybrid role requiring on-site ~2 days per week.

You will lead the design of high-speed networking ASICs, from specifications to netlist, with emphasis on Verilog/SystemVerilog, timing closure, and integration with physical design. You will mentor new engineers, collaborate with verification and PD teams, and contribute to architectural decisions.