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Hewlett Packard Enterprise Development LP is seeking a Senior ASIC Verification Engineer to lead VLSI verification efforts in a hybrid work model. You’ll design, validate and optimize complex ASIC blocks, mentor engineers, and collaborate with SW and logic teams to ensure robust chip solutions.
The role emphasizes SystemVerilog/UVM, formal verification, and advanced debugging across full-chip scope, with strong problem-solving and communication skills required.
Hewlett Packard Enterprise Development LP is seeking a Senior ASIC Verification Engineer to lead VLSI verification efforts in a hybrid work model. You’ll design, validate and optimize complex ASIC blocks, mentor engineers, and collaborate with SW and logic teams to ensure robust chip solutions.
The role emphasizes SystemVerilog/UVM, formal verification, and advanced debugging across full-chip scope, with strong problem-solving and communication skills required.