ASIC Verification Engineer

Enormous Enterprise LLC; Sunnyvale (CA); Hybrid; USD 140,000 - 180,000; Full time

Job summary

Enormous Enterprise LLC in Sunnyvale, CA is seeking a highly capable ASIC Verification Engineer to join our networking silicon development team. This hybrid role requires you to be in the office two days per week.

You will own block- or subsystem-level verification, develop robust UVM environments, and drive coverage closure across test plans. The role demands strong SystemVerilog, UVM, and waveform debugging skills to ensure high-quality ASIC/SoC deliverables.

Qualifications

• 5+ years of ASIC/SoC verification with ownership from test plan to coverage closure.
• Strong SystemVerilog and UVM expertise, building environments from scratch.
• Experience with test planning, coverage analysis, and debugging complex SoC designs.
• Proficiency with Cadence Xcelium, Synopsys VCS, Mentor Questa and waveform debugging.

Responsibilities

• Own block- or subsystem-level verification with test plans and coverage closure.
• Develop and maintain advanced UVM environments with agents, sequences, scoreboards.
• Perform constrained random testing and debug to achieve coverage goals.
• Analyze simulations using Cadence Xcelium, VCS, Questa and debug waveforms.
• Collaborate with cross-functional teams to deliver quality ASIC/SoC.

Skills

SystemVerilog & UVM

Constrained randomization

Functional coverage

SVA assertions

Test planning

Debugging SoC designs

Simulation workflow

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

UVM environments

Job description

Company

Enormous Enterprise LLC

Location

Sunnyvale, CA

Pay

DOE

Posted

September 09, 2026

ASIC Verification Engineer

Location: Sunnyvale, CA

Job Type: Full Time - Permanent

This is a Hybrid role based in Sunnyvale, CA with an expectation that you'll be in the office 2 days per week.

Position Summary

We are seeking a highly motivated ASIC Verification Engineer to join our networking silicon development team.

Key Responsibilities

• Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
• Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Required Skills And Qualifications

• 5+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
• Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
• Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
• Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
• Proficiency with industry-standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.

Preferred Skills And Experience

• Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
• Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
• Exposure to emulation environments, hardware acceleration, or traffic-model integration.
• Knowledge of coverage analytics, regression dashboards, and continuous-integration flows (e.g., Jenkins).
• Understanding of low-power (UPF) or formal verification methodologies.
• Own and drive block-level/subsystem/FullChip verification efforts, from creating test plans to achieving comprehensive coverage closure
• Experience with post-silicon bring-up and debug is a plus.
• Familiarity with emulation environments and debug flows is desirable.