Hybrid Senior ASIC Verification Engineer

Hewlett Packard Enterprise Company; Sunnyvale (CA); Hybrid; USD 159,000 - 321,000; Full time

Job summary

Hewlett Packard Enterprise invites a Senior ASIC Verification Engineer to join our dynamic team in Sunnyvale, CA on a hybrid schedule requiring ~2 days in office weekly. You will design, verify and validate VLSI blocks, build test benches in SystemVerilog/UVM, and collaborate with logic and software teams to deliver robust chips and platforms.

This role offers opportunities to influence product architectures and advance your expertise in cutting‑edge verification techniques.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent.
• 6-10 years of experience in VLSI design, verification, or implementation.
• Strong knowledge of SystemVerilog/UVM and verification methodologies.

Responsibilities

• Provide technical leadership for VLSI design and verification across modules and teams.
• Review designs for compliance with VLSI guidelines and standards.
• Develop test plans and write tests using SystemVerilog/C/C++ for architectural validation.
• Collaborate with logic designers and SW engineers to debug and optimize.
• Mentor junior engineers and interns.

Skills

VLSI design

SystemVerilog

UVM

C/C++

Python

Verilog

Education

Bachelor's or Master's degree in Electrical or Computer Engineering

Tools

SystemVerilog

UVM

Job description

Hewlett Packard Enterprise invites a Senior ASIC Verification Engineer to join our dynamic team in Sunnyvale, CA on a hybrid schedule requiring ~2 days in office weekly. You will design, verify and validate VLSI blocks, build test benches in SystemVerilog/UVM, and collaborate with logic and software teams to deliver robust chips and platforms.

This role offers opportunities to influence product architectures and advance your expertise in cutting‑edge verification techniques.