Senior ASIC Verification Engineer – Networking (Hybrid)

Hewlett Packard Enterprise; Sunnyvale (CA); Hybrid; USD 154,000 - 311,000; Full time

Job summary

Hewlett Packard Enterprise in Sunnyvale, CA is seeking a Senior ASIC Verification Engineer to join our networking silicon development team. This hybrid role requires in-office presence two days a week and offers exposure to advanced SoC verification in a fast-paced environment.

You will drive block- and subsystem verification, develop UVM environments, and collaborate with cross-functional teams to deliver high-quality ASIC/SoC results. Extensive experience with SystemVerilog is required.

Qualifications

• 10+ years of ASIC/SoC verification experience with test plan to coverage closure.
• Strong SystemVerilog and UVM expertise.
• Experience with randomization, constraints, coverage, and assertions

Responsibilities

• Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
• Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Skills

SystemVerilog

UVM methodology

Randomization

Test planning

Coverage analysis

Debugging

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

Hewlett Packard Enterprise in Sunnyvale, CA is seeking a Senior ASIC Verification Engineer to join our networking silicon development team. This hybrid role requires in-office presence two days a week and offers exposure to advanced SoC verification in a fast-paced environment.

You will drive block- and subsystem verification, develop UVM environments, and collaborate with cross-functional teams to deliver high-quality ASIC/SoC results. Extensive experience with SystemVerilog is required.