Hybrid ASIC Verification Engineer – Networking & SoCs

Hewlett Packard Enterprise Development LP; Sunnyvale, Northern (CA, KY); Híbrido; USD 124 000 - 251 000; Tempo integral

Resumo da oferta

Hewlett Packard Enterprise Development LP in Sunnyvale, CA, seeks a seasoned ASIC Verification Engineer to lead block‑level verification and own validation from test plans to coverage closure. You will build and maintain advanced UVM environments, run constraint-driven tests, and debug complex SoCs using Cadence Xcelium and other major simulators.

Ideal candidates bring 7+ years of relevant experience, strong SystemVerilog/UVM skills, and a deep understanding of coverage, randomization, and SVA.

Qualificações

• 7+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
• Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
• Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
• Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
• Proficiency with industry-standard simulation tools (Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.

Responsabilidades

• Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry-leading simulation tools and debug waveforms to validate design functionality.
• Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Conhecimentos

SystemVerilog

UVM

Deep knowledge of randomization

Assertions (SVA)

Test planning

Debugging complex SoCs

Ferramentas

Cadence Xcelium

Synopsys VCS

Mentor Questa

Descrição da oferta de emprego

Hewlett Packard Enterprise Development LP in Sunnyvale, CA, seeks a seasoned ASIC Verification Engineer to lead block‑level verification and own validation from test plans to coverage closure. You will build and maintain advanced UVM environments, run constraint-driven tests, and debug complex SoCs using Cadence Xcelium and other major simulators.

Ideal candidates bring 7+ years of relevant experience, strong SystemVerilog/UVM skills, and a deep understanding of coverage, randomization, and SVA.